Scan design is a method of structural design for testability for sequential circuits. This method changes the flip-flops in the circuit into controllable and observable ones, and connects the flip-flops into one or more shift registers to construct one or more scan chains. Using full scan design, one can convert sequential circuit test generation into combinational circuit test generation, and can drastically decrease the test generation cost and complete fault coverage. Thus, scan design is the most popular technique used in industry and academy. However, scan design increases the test application cost and test power consumption drastically. Some methods have been proposed to reduce test application cost and test power consumption for scan design, but none of those methods can obtain satisfactory results. Currently those methods includes:
(1) ordering test vectors or scan flip-flops. For example, the parity scan testing scheme proposed by Fujiwara. The methods can decrease the test application cost to a certain extent. However, test application cost may still be very high. Along with the increasing IC size, the test application time will be very long and these methods are unable to handle the problem.
(2) parallel scan. The method can decrease the test application time, but it brings to the problem of pin overhead. If we construct k scan chains in the circuit, we will have to use 2k+1 extra pins to input the scan pattern.
(3) controlling multiple scan chains by a single scan-in signal can reduce the test application time of system on a chip (SOC) to a great extent, but the test application time and test power of this method are still much greater than those of non-scan method.
(4) driving multiple scan chains with a single scan-in signal can reduce the test application time greatly, but it brings to an obvious degradation on fault coverage.
(5) using hybrid test generation algorithms to reduce test application cost. Experiments have proved that all these methods' contribution in reducing test application time is very limited.
Thus, how to decrease the test cost of scan design while remaining complete fault coverage has become an imminent problem and need to be solved as soon as possible.